1. Field of the Invention
The present invention relates to a driving circuit in a liquid crystal display (LCD), and more particularly, to a driving circuit of a shift register circuit in the liquid crystal display.
2. Description of the Related Art
Driving circuits formed on glass bases of liquid crystal displays (LCD) have become a main technology for the future LCD. The advantage thereof is to cost down the driving circuit. FIG. 1 shows a driving circuit of a single shift register unit of a conventional shift register. FIG. 2 is a timing diagram illustrating a driving circuit of the conventional shift register. For simplification, only the driving circuit of the single shift register unit and operation thereof are discussed here.
The conventional shift register circuit uses next stage output signal S(N+1) as a pull down signal of this stage. Pull down system 101 and pull down system 102 are electrically coupled between switch element T22 and low voltage VS for pulling down a voltage of switch element T22, respectively, when clock signals are CK and XCK. When switch element T23 receives a high voltage level clock signal XCK (period t2 in FIG. 2), switch element T23 is turned on and the high voltage level of clock signal XCK is transmitted to control terminal a of switch element T32. At this moment, switch element T32 is turned on. The high voltage level of next stage output signal S(N+1) is transmitted to control terminal b of switch element T30 to turn on switch elements T30 and T29. A control terminal of switch element T22 and this stage output terminal are pulled down to low voltage VS to ensure that output signal S(N) is off status during period T2.
However, the convention pull down mechanism uses next stage output signal S(N+1) to pull down this stage shift register unit. Because next stage output signal S(N+1) has only one duty cycle to pull down shift register unit (period t2 shown in FIG. 2), charges stored in coupled capacitors of switch element T22 cannot be fully discharged. Output signal S(N) is thus unstable when off status and generates voltage drift. In addition, due to the pull down mechanism in period T2, the control terminal of switch element T32 under high voltage clock signal XCK negatively affects switch element T32. Output signal S(N) cannot maintain its off status. Thus, an incorrect image may be displayed on the LCD.